1. Field of Invention
This invention is in the field of re-configurable hybrid assemblies on low loss substrates.
2. Description of the Related Art
Monolithic Integrated Circuits (MMIC) technology is a technology supporting many of the present generation of military and commercial radio frequency sensors and communication applications. MMICs include active devices, such as Field Effect Transistors and bipolar transistors, passive elements such as MIM capacitors, thin film and bulk resistors and inductors integrated on a single semi-insulating Gallium Arsenide substrate. Circuit performance and topology is generally fixed at the time of manufacture, typically using xe2x80x9cstaticxe2x80x9d impedance matching networks to interconnect various elements. This static approach limits a circuit to a single function, precludes its re-configuration, restricts its use for new modes, functions, operations and band-width. This inability to adapt to new configurations in real time to new requirements limits system performance, decreases system mean time between failure as well as useful operating lifetime, and flexibility.
Micro-Electro-Mechanical Systems (MEMS) is the integration of mechanical elements, sensors, actuators, and electronics on a common substrate through the utilization of microfabrication technology. While typical electronics elements such as transistors are fabricated using integrated circuit (IC) process sequences (e.g., CMOS, Bipolar, or BICMOS processes), micromechanical MEMS structures are fabricated using process compatible micromachining processes that selectively etch away parts of the silicon wafer or add new structural layers to form the mechanical and electromechanical devices.
An example of a MEMS structure having a bidirectional rotating member having two positions is described in U.S. Pat. No. 6,072,686, incorporated herein by reference in its entirety.
Another example of a MEMS structure for microwave (millimeter wave) applications is described in U.S. Pat. No. 6,046,659, incorporated herein by reference in its entirety.
A first MEM 329 having a first contact and a second contact is mounted on a substrate 301. A PA power cell 325 is thermally connected to the same substrate 301 using a thermal bump 321. The power cell 325 is electrically insulated from the substrate 301. The power cell 325 has a first power cell bump 311 and a second power cell bump 309 as pathways for I/O functions.
A first insulator 319 is mounted on substrate 301 supporting a second MEM 327 above the substrate 301. The second MEM 327 has a first connection 315 and a second connection 317. The first connection and the second connection are located on a bottom surface of the second MEM 327.
A first conductive via 313 vertically traverses the first insulator 319 and is connected to the first connection 315 from the second MEM 327. This first conductive via 313 is further connected to a first conductor 337. The first conductor is insulated from substrate 301 by a first insulating layer 333. The first conductor 337 is further connected to the first power cell bump 311.
A second conductor 335 is insulated from the substrate 301 by a second insulating layer 331. The second conductor 335 is connected to a second conductive via 307. The second conductive via 307 traverses vertically a second insulator 339. The second conductive via 307 is connected to a first metal member 305. The first metal member 305 is formed over the upper surface of the second insulator 339 and connected to a first input to the first MEM switch 329.
A second metal member 303 is connected to the second contact of the first MEM switch 329. The second metal member is formed over the upper surface of a third insulator 323. The third insulator 323 is positioned over substrate 301.